The present invention relates to a semiconductor device, a method of manufacturing the same, a circuit board, and an electronic instrument.
FIG. 15 is a plan view schematically showing a configuration of a conventional chip size package. FIG. 16 is a cross-sectional view of the chip size package shown in FIG. 15 taken along the line XVI—XVI. An interconnect layer 122 connected with an active region is formed on a semiconductor device 121, and pads 123 are formed on the interconnect layer 122. A stress relief layer 124 is formed on the active region of the semiconductor device 121 so that the pads 123 are exposed. A wiring pattern 125 is formed from the top of the pad 123 so as to extend onto the stress relief layer 124. A solder resist film 126 is formed on the wiring pattern 125. An opening 127 which exposes a part of the wiring pattern 125 on the stress relief layer 124 is formed in the solder resist film 126. A solder ball 128 is formed on the wiring pattern 125 through the opening 127. The stress relief layer 124 and the solder resist film 126 are formed of a resin.
Therefore, since the resin layer is formed over a wide area of the semiconductor device 121, it is difficult to prevent warping of the semiconductor device 121 which occurs due to internal stress of the resin layer.